View U4256BM-RSG3_1330221.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* * * * * * * * * * *
Reference Oscillator up to 15 MHz (Tuned) Oscillator Buffer Output (for AM Up/Down Conversion) Two Programmable 16-bit Dividers Fine-tuning Steps Possible Fast Response Time due to Integrated Loop Push-pull Stage 3-wire Bus (Enable, Clock and Data; 3 V and 5 V Microcontrollers Acceptable) Four Programmable Switching Outputs (Open Drain) Three DACs for Software Controlled Tuner Alignment Low-power Consumption High S/N Ratio Integrated Band Gap - only One Supply Voltage Necessary
Description
The U4256BM-R is a synthesizer IC for FM receivers and an AM up-convertion system in BICMOS technology. Together with the AM/FM IC T4258 or U4255BM, it performs a complete AM/FM car radio front-end, which is recommended also for RDS (Radio Data System) applications. It is controlled by a 3-wire bus and also contains switches and Digital to Analog Converters (DACs) for software-controlled alignment of the AM/FM tuner. The U4256BM-R is the pin-compatible succesor IC of U4256BM-N.
Frequency Synthesizer for Radio Tuning U4256BM-R Preliminary
Pin Configuration
Figure 1. Pinning SSO20
FMOSCIN OSCOUT 12 SWO3 9
GNDan
MX2LO
OSCIN
DATA
CLK
20
19
18
17
16
15
U4256BM-R
14
13
DAC1
SWO4 10
1
4
5
2
3
SWO1 7
PD
6
SWO2
DAC2
PDO
DAC3
VS
8
11 GND
EN
V5
Rev. 4562C-AUDR-08/04
1
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol PDO PD DAC1 DAC2 DAC3 VS SWO1 SWO2 SWO3 SWO4 GND OSCOUT OSCIN V5 MX2LO DATA CLK EN FMOSCIN GNDan Function Phase detector output Pulsed current output Digital-to-analog converter 1 Digital-to-analog converter 2 Digital-to-analog converter 3 Supply voltage analog part Switching output 1 Switching output 2 Switching output 3 Switching output 4 Ground, digital part Reference oscillator output Reference oscillator input Capacitor band gap Oscillator buffer output Data input Clock Enable FM-oscillator input Ground, analog part
Figure 2. Block Diagram
SWO1 SWO2 SWO3 SWO4 7 Tuning 13 12 Oscillator Switching outputs DAC3 3-bit V Ref 4 5 8 9 10
OSCIN OSCOUT
DAC3
MX2LO
15
OSC buffer
CLK DATA EN
17 16 18 3Wbus interface
DAC2
DAC2
DAC1
3
DAC1
Rdivider
DAC AM/FM
V
Ref
FMOSCIN
19
FMpreamp
Ndivider
Phase detector
Current sources
1
PDO
Bandgap 20 GNDan V5 14 11 GND VS 6
2
PD
2
U4256BM-R
4562C-AUDR-08/04
U4256BM-R
Functional Description
For a tuned FM-broadcast receiver, the following parts are needed: * * * Voltage-Controlled Oscillator (VCO) Antenna Amplifier Tuned Circuit RF Amplifier Tuned Circuit
Typical modern receivers with electronic tuning are tuned to the desired FM frequency by the frequency synthesizer IC U4256BM-R. The special design allows the user to build software-controlled tuner alignment systems. Two programmable DACs (Digital-toAnalog Converter) support the computer-controlled alignment. The output of the PLL is a tuning voltage which is connected to the VCO of the receiver IC. The output of the VCO is equal to the desired station frequency plus the IF (10.7 MHz). The RF and the oscillator signal (VCO) are both input to the mixer that translates the desired FM channel signal to the fixed IF signal. For FM, the double-conversion system of the receiver requires exactly 10.7 MHz for the first IF frequency, which determines the center frequency of the software-controlled integrated second IF filter. If this oscillator tuning feature is not used, the internal capacities have to be switched off and the oscillator has to be operated with high-quality external capacities to ensure that the operational frequency is exactly 10.250 MHz. When dimensioning the oscillator circuit, it is important that the additional capacities enable the oscillator to operate through its complete tracking range. The oscillating ability depends very strongly on the used crystal oscillator. Initializing the oscillator should be established without switching any additional capacities to guarantee that the oscillator starts to operate properly. Due to the lower quality of the integrated capacities compared to discrete capacities, the amount of the switched integrated capacities should always be minimized. (If necessary reduce tracking range or use another crystal oscillator.) The U4256BM-R has a very fast response time of maximum 800 s (at 2 mA, fStep = 50 kHz, measured on MPX signal). It performs a high signal to noise ratio. Only one supply voltage is necessary, due to a integrated band gap.
Input/Output Interface Circuits
PDO (Pin 1) PD (Pin 2)
PDO is the buffer amplifier output of the PLL. The bipolar output stage is a rail-to-rail amplifier. PD is the current charge pump output of the PLL. The current can be controlled by setting the Bits. The loop filter has to be designed corresponding to the choosen pump current and the internal reference frequency. A recommendation can be found in the application circuit. The charge-pump current can be choosen by setting the Bits 71 and 70 as following:
IPD (A) 25 100 500 2000 B71 0 0 1 1 B70 0 1 0 1
3
4562C-AUDR-08/04
Figure 3. Internal Components at PDO Connection
VS VS
VS PDO PD
FMOSCIN (Pin 19)
FMOSCIN is the preamplifier input for the FM oscillator signal. Figure 4. Internal Components at FMOSCIN
V5
FMOSCIN
MX2LO (Pin 15)
MX2LO is the buffered output of the crystal oscillator. This signal can be used as a reference frequency for U4255BM or T4258. The oscillator buffer output can be switched by the OSCB Bit as following (Bit 69)
MX2LO AC Voltage ON OFF B69 0 1
Figure 5. Internal Components at MX2LO
V5 V5
OSCIN MX2LO
4
U4256BM-R
4562C-AUDR-08/04
U4256BM-R
Function of DAC1, 2 in FM and AM Mode (Pin 3 and Pin 4)
For automatic tuner alignment, the DAC1 and DAC2 of the U4256BM-R can be controlled by setting gain of VPDO and offset values. The following figure shows the principle of the operation. In FM Mode the gain is in the range of 0.69 x V(PDO) to 2.16 x V(PDO). The offset range is +0.56 V to -0.59 V. For alignment, DAC1 and DAC2 are connected to the varicaps of the preselection filters. For alignment, offset and gain is set for having the best tuner tracking. Figure 6. Principle Operation for Alignment
Bit 34 PDO (FM) DAC1,2
Gain
+/-
Vref (AM) (3 V) Offset
The DAC mode can be controlled by setting the Bit 34 as following:
DAC Mode FM AM B34 0 1
If Bit 34 = 1 (AM Mode), the DAC1, DAC2 can be used as standard DAC converters. The internal voltage of 3 V is connected to the gain- and offset-input of DAC1 and DAC2 (only in AM Mode). The gain is in the range of 0.46 x 3 V to 3.03 x 3 V. The offset range is +1.46 V to -1.49 V. Figure 7. Internal Components at DAC1,2 Output
VS
DAC1,2
5
4562C-AUDR-08/04
DAC 1, 2 in FM Mode (Pin 3 and Pin 4)
The gains of DAC1 and DAC2 have a range of 0.69 x V(PDO) to 2.16 x V(PDO). V(PDO) is the PLL tuning voltage output. This range is divided into 256 steps. So one step is approximately (2.16 - 0.46) x V(PDO) / 255 = 0.005764 x V(PDO). The gain of DAC1 can be controlled by the Bits 36 to 43 (G-20 to G-27) and the gain of DAC2 by the Bits 0 to 7 (G20 to G-27) as following:
Gain DAC1 Approximately Gain DAC2 Approximately 0.69 x V(PDO) B43 B7 0 B42 B6 0 B41 B5 0 B40 B4 0 B39 B3 0 B38 B2 0 B37 B1 0 B36 B0 0 Decimal Gain Decimal Gain 0
0.69576 x V(PDO) 0.70153 x V(PDO) 0.70729 x V(PDO) ... 0.99549 x V(PDO) ... 2.14847 x V(PDO) 2.15424 x V(PDO) 2.16 x V(PDO)
0 0 0 ... 0 ... 1 1 1
0 0 0 ... 0 ... 1 1 1
0 0 0 ... 1 ... 1 1 1
0 0 0 ... 1 ... 1 1 1
0 0 0 ... 0 ... 1 1 1
0 0 0 ... 1 ... 1 1 1
0 1 1 ... 0 ... 0 1 1
1 0 1 ... 1 ... 1 0 1
1 2 3 ... 53 ... 253 254 255
Offset = 31 (intermediate position) The offset of DAC1 and DAC2 has a range of 0.56 V to -0.59 V. This range is divided into 64 steps. So one step is approximately 1.15 V/ 63 = 18.25 mV. The offset DAC1 can be controlled by the Bits 44 to 49 (O-20 to O-25) and the offset of DAC2 by the Bits 8 to 13 (O-20 to O-25) as following:
Offset DAC1 Approximately Offset DAC2 Approximately 0.56 V B49 B13 0 B48 B12 0 B47 B11 0 B46 B10 0 B45 B9 0 B44 B8 0 Decimal Gain Decimal Gain 0
0.5417 V 0.5235 V 0.5052 V ... +0.0059 V ... 0.5535 V -0.5717 V -0.59 V
0 0 0 ... 0 ... 1 1 1
0 0 0 ... 1 ... 1 1 1
0 0 0 ... 1 ... 1 1 1
0 0 0 ... 1 ... 1 1 1
0 1 1 ... 1 ... 0 1 1
1 0 1 ... 1 ... 1 0 1
1 2 3 ... 31 ... 61 62 63
Gain = 53 (intermediate position)
6
U4256BM-R
4562C-AUDR-08/04
U4256BM-R
DAC 1, 2 in AM Mode (Pin 3 and Pin 4)
In AM mode the DAC input voltage V(PDO) is internal connected to 3 V. The gains of DAC1 and DAC2 have a range of 0.46 x 3 V to 3.03 x 3 V. V(PDO) is the PLL tuning voltage output. This range is divided into 256 steps. So one step is approximately (3.03 - 0.46) x 3 V/255 = 0.01007 x 3 V. The gain of DAC1 can be controlled by the Bits 36 to 43 (G-2 0 to G-2 7 ) and the gain of DAC2 by the Bits 0 to 7 (G-2 0 to G-2 7 ) as following:
Gain DAC1 Approximately Gain DAC2 Approximately 0.4607 x 3 V B43 B7 0 B42 B6 0 B41 B5 0 B40 B4 0 B39 B3 0 B38 B2 0 B37 B1 0 B36 B0 0 Decimal Gain Decimal Gain 0
0.4710 x 0.4812 x 0.4915 x ... 1.0029 x ... 3.0097 x 3.0196 x 3.0296 x
3V 3V 3V 3V 3V 3V 3V
0 0 0 ... 0 ... 1 1 1
0 0 0 ... 0 ... 1 1 1
0 0 0 ... 1 ... 1 1 1
0 0 0 ... 1 ... 1 1 1
0 0 0 ... 0 ... 1 1 1
0 0 0 ... 1 ... 1 1 1
0 1 1 ... 0 ... 0 1 1
1 0 1 ... 1 ... 1 0 1
1 2 3 ... 53 ... 253 254 255
Offset = 31 (intermediate position) Remark: V(PDO) is 3 V in AM mode. The offset of DAC1 and DAC2 has a range of +1.46 V to -1.49 V. This range is divided into 64 steps. So one step is approximately 2.95 V/ 63 = 46.8 mV. The offset DAC1 can be controlled by the Bits 44 to 49 (O-20 to O-25) and the offset of DAC2 by the Bits 8 to 13 (O-20 to O-25) as following:
Offset DAC1 Approximately Offset DAC2 Approximately 1.4606 V B49 B13 0 B48 B12 0 B47 B11 0 B46 B10 0 B45 B9 0 B44 B8 0 Decimal Gain Decimal Gain 0
1.4138 V 1.3665 V 1.3196 V ... -0.0079 V ... -1.3975 V -1.4447 V -1.4917 V
0 0 0 ... 0 ... 1 1 1
0 0 0 ... 1 ... 1 1 1
0 0 0 ... 1 ... 1 1 1
0 0 0 ... 1 ... 1 1 1
0 1 1 ... 1 ... 0 1 1
1 0 1 ... 1 ... 1 0 1
1 2 3 ... 31 ... 61 62 63
Gain = 53 (intermediate position)
7
4562C-AUDR-08/04
DAC3 (Pin 5)
The DAC3 output voltage can be controlled by the Bits P-20 to P-22 (Bits 66 to 68) as following:
DAC3 Offset Approximately B68 B67 B66
0.55 V 1.25 V 1.90 V 2.60 V 3.30 V 4.10 V 4.80 V 5.45 V
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Figure 8. Internal Components at DAC3
VS
DAC3
EN, DATA, CLK (Pin 16-18)
All functions can be controlled via a 3-wire bus consisting of ENABLE, DATA and CLOCK. The bus is designed for microcontrollers which operate with 3 V supply voltage. Details of the data transfer protocol are shown in the table `3-wire Bus Description'. Figure 9. Internal Components at EN, DATA, CLK
V5
EN DATA CLK
8
U4256BM-R
4562C-AUDR-08/04
U4256BM-R
SWO1, 2, 3 and 4 (Pin 7-10)
All switching outputs are `open drain' and can be set and reset by software control. Details are described in the data transfer protocol. The switching output SWO1 to SWO4 can be controlled as following (Bits 30 to 33):
Switch Output B30 + X
SWOx = ON (switch to GND) SWOx = OFF
0 1
X = 0 to 3 Figure 10. Internal Components at SWO1, 2, 3 and 4
SWO1 SWO2 SWO3 SWO4 I
OSCIN, OSCOUT (Pin 12 and Pin 13)
A crystal resonator (up to 15 MHz) is connected between OSCIN and OSCOUT in order to generate the reference frequency. By using the U4256BM-R in connection with U4255BM or T4258, the crystal frequency must be 10.25 MHz. The complete application circuit is shown in Figure 15. If a reference is available, it can be applied at OSCIN. The minimum voltage should be 100 mVrms. In this case, Pin OSCOUT has to be open. The tuning capacity for the crystal oscillator has a range of 0.5 pF to 71.5 pF. The values are coded binary. The tuning can be controlled by the Bits 78 to 85 as following:
B85 = 1 [pF] B85 = 0 [pF] B84 B83 B82 B81 B80 B79 B78
0 0.5 1.0 1.5 ... 63.0 63.5
8.0 8.5 9.0 19.5 ... 71.0 71.5
1 1 1 1 ... 0 0
1 1 1 1 ... 0 0
1 1 1 1 ... 0 0
1 1 1 1 ... 0 0
1 1 1 1 ... 0 0
1 1 0 0 ... 0 0
1 0 1 0 ... 0 0
9
4562C-AUDR-08/04
Figure 11. Internal Components at OSCIN and OSCOUT
V5
OSCIN
V5
OSCOUT
Figure 12. Internal Connection of Tuning Capacity for Crystal Oscillator
Cx1 Cx2
INV 8pF 32pF ... 0.5 pF 0.5 pF ... 32pF 8pF
B78 B84 B85
10
U4256BM-R
4562C-AUDR-08/04
U4256BM-R
Application Information
Figure 13. FMOSCIN Sensitivity
Vi (mVrms on 50 ) 150
100
50
0 0 20 40 60 80 100 120 Frequency (MHz) 140 160
3-wire Bus Description
The register settings of U4256BM-R are programmed by a 3-wire bus protocol. The bus protocol consists of separate commands. A defined number of bits is transmitted sequentially during each command. One command is used to program all the bits of one register. The different registers available (see table Data Transfer) are addressed by the length of the command (number of transmitted bits) and by two address bits, that are unique to each register of a given length. 16-bit registers are programmed by 16-bit commands and 24-bit registers are programmed by 24-bit commands. Each bus command starts with a rising edge on the enable line (EN) and ends with a falling edge on EN. EN has to be kept HIGH during the bus command. The sequence of transmitted bits during one command starts with the LSB of the first byte and ends with the MSB of the last byte of the register addressed. To transmit one bit (0/1) DATA has to be set to the appropriate value (LOW/HIGH) and a LOW to HIGH transition has to be performed on the clock line (CLK) while DATA is valid. The DATA is evaluated at the rising edges of CLK. The number of LOW to HIGH transitions on CLK during the HIGH period of EN is used to determine the length of the command. The bus protocol and the register addressing of U4256BM-R are compatible to the addressing used in U4255BM and T4258. That means U4256BM-R and U4255BM (or T4258) can be operated on the same 3-wire bus as shown in the application circuit.
11
4562C-AUDR-08/04
Figure 14. 3-wire Bus Timing Diagram tR Enable tS tR Data tHDA tS tR Clock tF VHIGH VLOW tH tL tF VHIGH VLOW tHEN tF VHIGH VLOW
Figure 15. 3-wire Pulse Diagram
16-bit command
EN DATA CLK
LSB BYTE 1 MSB LSB BYTE 2 MSB
24-bit command
EN DATA CLK
LSB BYTE 1 MSB LSB BYTE 2 MSB LSB BYTE 3 MSB
e.g. R-Divider
20 21 22 23 24 25 26 27 28 29 2 10 2 11 2 12 2 13 2 14 2 15
0
P-2
P-2 2 P-2
1
OSCB
IPD
0
0
R-Divider
DAC3
Status 0
Addr.
12
U4256BM-R
4562C-AUDR-08/04
U4256BM-R
Data Transfer
Table 1. Control Registers
A
MSB ADDR. 0 0 B71 BYTE 3 STATUS 0 IPD B70 OSCB 0=on, 1=off B69 P-22 B68 DAC3 P-21 B67 P-20 B66 215 B65 214 B64 213 B63 212 B62 210 B61 211 B60 29 B59 LSB MSB BYTE 2 LSB MSB BYTE 1 LSB
R-Divider 28 B58 27 B57 26 B56 25 B55 24 B54 23 B53 22 B52 21 B51 20 B50
B
MSB ADDR. 0 1 0 B35 BYTE 3 STATUS 1 AM=1 SWO4 SWO3 SWO2 SWO1 FM=0 0=on, 0=on, 0=on, 0=on, DAC 1=off 1=off 1=off 1=off B34 B33 B32 B31 B30 215 B29 214 B28 213 B27 212 B26 210 B25 211 B24 29 B23 LSB MSB BYTE 2 LSB MSB BYTE 1 LSB
N-Divider 28 B22 27 B21 26 B20 25 B19 24 B18 23 B17 22 B16 21 B15 20 B14
C
MSB ADDR. 0 0 O-25 B49 O-24 B48 BYTE 2 DAC1 OFFSET O-23 B47 O-22 B46 O-21 B45 O-20 B44 G-27 B43 G-26 B42 G-27 B41 LSB MSB BYTE 1 DAC1 GAIN G-25 B40 G-24 B39 G-23 B38 G-22 B37 G-20 B36 LSB
D
MSB ADDR. 0 1 O-25 B13 O-24 B12 BYTE 2 DAC2 OFFSET O-23 B11 O-22 B10 O-21 B9 O-20 B8 G-27 B7 G-26 B6 G-27 B5 LSB MSB BYTE 1 DAC2 GAIN G-25 B4 G-24 B3 G-23 B2 G-22 B1 G-20 B0 LSB
E
MSB ADDR. 1 0 8pF B85 32pF B84 BYTE 2 LSB Oscillator tuning function 16pF B83 8pF B82 4pF B81 2pF B80 1pF B79 0.5pF B78 X B77 X B76 MSB BYTE 1 Not used X B75 X B74 X B73 X B72 LSB
Absolute Maximum Ratings
Parameters Symbol Value Unit
Analog supply voltage Input voltage BUS Output current switches (see Figure 10) Drain voltage switches Storage temperature range Junction temperature Electrostatic handling M.M. Ambient temperature range
Pin 6 Pins 16, 17 and 18 Pins 7, 8, 9 and 10 Pins 7, 8, 9 and 10
VS VI IO VOD Tamb Tstg Tj VESD
8 to 12 -0.3 to +5.3 -1 to +5 15 -40 to +85 -40 to +125 125 300
V V mA V
C C C
V
13
4562C-AUDR-08/04
Thermal Resistance
Parameters Symbol Value Unit
Junction ambient, when soldering to PCB
RthJA
140
K/W
Operating Range
All voltages are referred to GND (Pin 11)
Parameters Symbol Min. Typ. Max. Unit
Supply voltage range Ambient temperature Input frequency FMOSCIN Programmable N, R divider Crystal reference oscillator
Pin 6 Pin 19 Pins 12 and 13
VS Tamb fin SF fXTAL
8 -40 70 2 0.1
8.5
12 +85 160 65535 15
V C MHz MHz
Electrical Characteristics
Test Conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25C.
No. 1 Parameters Supply Voltage Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1.1
2
Analog supply voltage
Supply Current
6 6 f = 0.1 to 15 MHz At Pin15: 47 pF and 1 k 13
VS IS OSC
8 5 100
8.5 10
12 25
V mA mVrms
A A B
2.1
3
Analog supply current
OSCIN
3.1
4
Input voltage
OSC Buffer (MX2LO)
4.1 4.2
5
Output AC voltage Output DC voltage
FMOSCIN
15 15
vMX2LO VMX2LO FMOSC FMOSC
80 1.8 40 150
120 2.0
200 2.2
mVpp V mVrms mVrms
B A
5.1
6
Input voltage
f = 70 to 120 MHz f = 120 to 160 MHz PD = 2.5 V PD = 2.5 V PD = 2.5 V PD = 2.5 V PD = 2.5 V
19
B
Pulsed Current Output PD
6.1 6.2 6.3 6.4 6.5
Output current Bit 71, 70 = `00' Output current Bit 71, 70 = `01' Output current Bit 71, 70 = `10' Output current Bit 71, 70 = `11' Leakage current
2 2 2 2 2
IPD IPD IPD IPD IPDL
20 80 400 1500
25 100 500 2000
30 120 600 2400 20
A A A A nA
A A A A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
14
U4256BM-R
4562C-AUDR-08/04
U4256BM-R
Electrical Characteristics (Continued)
Test Conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25C.
No. 7 Parameters PDO Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
7.1 7.2
8
Saturation voltage HIGH Saturation voltage LOW
SWO1, SWO2, SWO3, SWO4 (Open Drain)
3, 4 3, 4
8.0 0
8.5 0.4
V V
A A
8.1 8.2
9
Output leakage current HIGH Output voltage LOW
DAC1, DAC2
Pin 7,8,9,10 over R against 8.5 V I = 1 mA
7, 8, 9, 10 7, 8, 9, 10 3, 4 3, 4
ISWOH VSWOL 100
100 400
nA mV
A A
9.1 9.2 9.3 9.4 9.5 9.6
10
Output current Output voltage Maximum offset range (FM) Minimum offset range (FM) Maximum gain range (FM) Minimum gain range (FM)
DAC3
IDAC1, 2 VDAC1, 2 0.3 0.45 -0.45 0.63 2.1 0.56 -0.57 0.69 2.16
1
mA V V V
C A A A A A
VS-0.6 0.65 -0.65 0.75 2.23
offset = 0, gain = 53 offset = 63, gain = 53 gain = 255, offset = 31 gain = 0, offset = 31
3, 4 3, 4 3, 4 3, 4
10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9
11
Output current Output voltage Output voltage Output voltage Output voltage Output voltage Output voltage Output voltage Output voltage Input voltage HIGH LOW Clock frequency Period of CLK HIGH LOW Rise time EN, DATA, CLK Fall time EN, DATA, CLK Bit 68-66: 000 Bit 68-66: 001 Bit 68-66: 010 Bit 68-66: 011 Bit 68-66: 100 Bit 68-66: 101 Bit 68-66: 110 Bit 68-66: 111
5 5 5 5 5 5 5 5 5
IDAC3 VDAC3 VDAC3 VDAC3 VDAC3 VDAC3 VDAC3 VDAC3 VDAC3 VBUSH VBUSL tH tL tr tf 0.4 1.1 1.8 2.4 3.2 3.8 4.5 5.2 2.7 -0.3 250 250 0.55 1.25 1.90 2.60 3.30 4.10 4.80 5.45
1
mA V V V V V V V V V V MHz ns ns
C A A A A A A A A
0.7 1.4 2.1 2.8 3.5 4.3 5.0 5.7 5.3 0.8 1.0
3-wire Bus, ENABLE, DATA, CLOCK
11.1 11.2 11.3 11.4 11.5
16-18 17 17 16-18 16-18
A A D D D
400 100
ns ns
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
15
4562C-AUDR-08/04
Electrical Characteristics (Continued)
Test Conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25C.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
11.6 11.7 11.8
Set-up time Hold time EN Hold time DATA
16-18 18 16
ts tHEN tHDA
100 250 0
ns ns ns
D D D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Figure 16. Application Circuit
EN CLK DATA C 12 GND
100 nF
R5 5.1 k C8 47 pF 20 C1 10 pF fOSC FM VCO 1 Vtune R4 8.2 k C6 C 15 330 pF C 14 C7 10 nF 10 nF 10 nF 10 nF C4 100 nF 2 3 4 C 16 5 6 C5 7 DAC's R2 600 LOGIC 19 18 17 BUS 16 15 14
C9 *)
*) *) depends on crystal 10.25 MHz 13 12 OSC 11
Switches 8 9 10
100 mF R3 100
DAC1
DAC2
DAC3
VS 8 ... 12 V
SWO1
SWO2
SWO3
SWO4
16
U4256BM-R
4562C-AUDR-08/04
4562C-AUDR-08/04
R407 10 MULTIP DEV R34 27 KR202 X301 KF302 R305 1k5 C in F201 C307 C206 10n 220n C310 1n 30 29 28 27 26 25 24 23 C205 220n 33 32 31 10u 35 34 U4255BM 1 R313 390 47p 22p F131 C108 C109 1n 6p8 C107 D102 18p R121 68k BB804 R104 470 R112 47k 10p 27p T101 BFR93A F101 BB804 D101 C102 3p9 S391D 10n D103 C103 68k R122 C158 10n C159 10n R151 8k2 C152 330p C104 C56 10n C106 L102 2u2 D131 R131 5k6 20 C134 U4256BM 1n 1 2 3 C151 10n DAC3 SWO1 SWO3 SWO2 SWO4 C157 10n MPX ADJAC C115 100n C116 100n METER 4 5 6 7 8 9 10 19 18 17 16 15 14 BB804 C133 6p8 22u 220n C203 C114 C131C132 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 INT IF2OUT DATA CLK EN C156 10n C155 100n C153 C154 12p* 12p* 10,25MHz Q151 13 12 11 *depends on Q151 GND C207 220n C312 10n R152 10 C208 C309 F302 10n 1u C111 44 43 42 41 40 39 38 470n C204 470n 37 36 R111 200k C202 C113 100n 100p R303 1k R106 10 F201 C209 100n 10n C306 C112 10u C201 KR201 R304 1k3 R29 10 C308 100n VS (+8,5V...10,5V) R102 68k F102 C314 10n C110 4n7
L302
C319
100uH
6p8
12p
R311
Figure 17. Application Board Schematic
2k2
L303 2m2
R105 100
R115 1k
T102 BC858
T302 BC848
C316 R308 T301
220n
2k2
BC 858C
R306 470k
T111 J109
R307 47
C315 C302
220n 10n
C117
10n
L301
D301
4u7
Ant
S391D
FM 75 Ohm
D302
C311
U4256BM-R
S391D
100n
R103 1k
17
Ordering Information
Extended Type Number Package Remarks
U4256BM-RFS U4256BM-RSG3
SSO20 SSO20
Tube Taped and reeled
Package Information
Package SSO20
Dimensions in mm
6.75 6.50 5.7 5.3 4.5 4.3
1.30 0.25 0.65 5.85 20 11 0.15 0.05 0.15 6.6 6.3
technical drawings according to DIN specifications
1
10
18
U4256BM-R
4562C-AUDR-08/04
Atmel Headquarters
Corporate Headquarters
2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743
AAvenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
(c) Atmel Corporation 2003. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
Atmel (R) is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
4562C-AUDR-08/04 xM

▲Up To Search▲

Price & Availability of U4256BM-RSG3

	To Download U4256BM-RSG3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .